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p-dso-14-4 p-dso-20-6 dual low-drop voltage regulator tle 4470 semiconductor group 1 1998-11-01 functional description the tle 4470 is a monolithic integrated voltage regulator with two very low-drop outputs, a main output q2 for loads up to 350 ma and a stand by output q1 providing a maximum of 180 ma. the device is available in both the p-dso-14-4 and p-dso-20-6 packages. it is designed to supply microprocessor systems under the severe conditions of automotive applications and is therefore equipped with additional protection functions against over load, short circuit and over temperature. of course the tle 4470 can also be used in other applications where two stabilized voltages are required. the device operates in the wide temperature range of C 40 c to 150 c. the stand by regulator transforms an input voltage v i in the range of 5.6 v v i 45 v to v q1rated = 5 v within an accuracy of 2%, whereas the main regulator is adjustable. by use of an external voltage divider the main output voltage can be set to v q2 3 5 v for the type ordering code package tle 4470 gs Q67006-A9309 p-dso-14-4 (smd) tle 4470 g q67006-a9308 p-dso-20-6 (smd) features ? stand-by output 180 ma; 5 v 2% ? adjustable reset switching threshold ? main output 350 ma; tracked to the stand-by output ? low quiescent current consumption in standby mode ? disable function for main output ? wide operation range: up to 45 v ? very low dropout ? power-on-reset circuit sensing the stand-by voltage ? early warning comparator for supply undervoltage ? output protected against short circuit ? wide temperature range: C 40 c to 150 c ? over-temperature protection ? over-load protection
tle 4470 semiconductor group 2 1998-11-01 tle 4470 g type (p-dso-20-6 package). v q1 is compared to the voltage at pin va, which is proportional to the output voltage v q2 . a control amplifier drives the base of the series pnp transistor via a buffer. the main output voltage v q2 is tracked to the accuracy of the stand by output. for the tle 4470 gs (p-dso-14-4 package) the output voltage is fixed to 5 v. to save energy e.g. in battery powered body electronic applications, the main regulator can be switched off via the disable input, which causes the current consumption to drop to 180 m a typical. two additional features of the tle 4470 are an early warning comparator (can be used e.g. to monitor the supply voltage v i ) and reset generator with an adjustable reset delay time. the tle 4470 g (p-dso-20-6 package) has in addition an adjustable reset switching threshold. this feature is useful with microprocessors which guarantee a safe operation down to voltages below the internally set reset threshold of 4.65 v typical. two functions are included in the reset generator, a power on reset and an under-voltage reset. the power on reset feature is necessary for a defined start of the microprocessor when switching on the application. the reset low signal is generated for a certain delay time after the output voltage v q1 of the regulator has surpassed the reset threshold. an external delay capacitor sets the delay time. the under voltage reset circuit supervises the stand-by output voltage. in case v q1 falls below the reset switching threshold the reset output is set low after a short reaction time. the reset low signal is generated down to an output voltage v q1 of 1 v. pin configuration (top view) figure 1 gnd gnd 10 8 9 7 6 3 5 4 2 120 19 18 17 16 15 14 13 12 11 gnd dis d gnd rq si aep02151 sq gnd radj gnd gnd adj2 gnd q2 q2 q1 i i 1 2 gnd 7 6 3 5 4 2 114 13 12 11 10 9 8 gnd gnd dis si aep02152 gnd d i gnd gnd rq sq q2 q1 p-dso-20-6 p-dso-14-4
tle 4470 semiconductor group 3 1998-11-01 pin definitions and functions p-dso-20-6 pin no. symbol function 1radj reset switching threshold adjust ; for setting the reset switching threshold connect to a voltage divider from q1 to gnd. if this input is connected to gnd, the reset is triggered at the internal threshold. 2d reset delay ; connect a capacitor c d to gnd for delay time adjustment 3dis disable input main regulator ; q2 disabled with high signal 4, 5, 6, 7 gnd ground 8rq reset output ; the open collector output is connected to q1 via an integrated 30 k w resistor 9sq sense output ; the open collector output is connected to q1 via an integrated 30 k w resistor 10 q1 stand-by regulator output voltage ; block to gnd with a capacitor c q1 3 6 m f, esr < 10 w at 10 khz 11 adj2 main regulator adjust input ; q2 can be set to higher values by an external divider 12, 13 q2 main regulator output voltage ; block to gnd with a capacitor c q2 3 10 m f, esr < 10 w at 10 khz 14, 15, 16, 17 gnd ground 18 i2 main regulator input voltage ; block to gnd directly at the ic with a ceramic capacitor 19 i1 stand-by regulator input voltage ; block to gnd directly at the ic with a ceramic capacitor 20 si sense comparator input
tle 4470 semiconductor group 4 1998-11-01 radj reset switching threshold adjust not available in p-dso-14-4 package. reset is always triggered at the internal threshold. adj2 main regulator adjust input is internally connected to v q2 p-dso-14-4 pin no. symbol function 1d reset delay ; connect a capacitor c d to gnd for delay time adjustment 2dis disable input main regulator ; q2 disabled with high signal 3, 4, 5 gnd ground 6rq reset output ; the open collector output is connected to q1 via an integrated 30 k w resistor 7sq sense output ; the open collector output is connected to q1 via an integrated 30 k w resistor 8q1 stand-by regulator output voltage ; block to gnd with a capacitor, c q1 3 6 m f, esr < 10 w at 10 khz 9q2 main regulator output voltage ; 5 v output tracking to q1, block to gnd with a capacitor c q2 3 10 m f, esr < 10 w at 10 khz 10, 11, 12 gnd ground 13 i main and stand-by regulator input voltage ; block to gnd directly at the ic with a ceramic capacitor 14 si sense comparator input
tle 4470 semiconductor group 5 1998-11-01 figure 2 block diagram reference stand-by-regulator main regulator = reset = sense 19 18 3 20 10 13 11 2 8 1 9 14-17 12, 4-7 d rq radj sq gnd adj2 dis si 30 k w w 30 k q1 v aeb02153 i 1 v ref i d radjth v ref v v sith 2 i q2 q1 pin numbers valid for p-dso-20-6 (tle 4470 g)
tle 4470 semiconductor group 6 1998-11-01 absolute maximum ratings C 40 c < t j < 150 c parameter symbol limit values unit remarks min. max. stand-by regulator input voltage v i 1 voltage v i 1 C 42 45 v C current i i 1 C C ma internally limited main regulator input voltage v i 2 voltage v i 2 C 42 45 v C current i i 2 C C ma internally limited stand-by output v q1 voltage v q1 C 1 7 v C current i q1 C C ma internally limited main output v q2 voltage v q2 C 1 36 v C current i q2 C C ma internally limited main regulator adjust input adj2 voltage v adj2 C 0.3 18 v C current i adj2 C C ma internally limited sense output sq voltage v sq C 0.3 25 v C current i sq C 5 5 ma C reset output rq voltage v rq C 0.3 25 v C current i rq C 5 5 ma C
tle 4470 semiconductor group 7 1998-11-01 note: esd-protection according to mil std. 883: 2 kv. maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. disable input dis voltage v dis C 42 45 v C current i dis C 2 2 ma C sense input si voltage v si C 25 18 v C current i si C 2 2 ma C reset delay d voltage v d C 0.3 7 v C current i d C 2 2 ma C reset switching threshold adjust radj voltage v radj C 0.3 7 v C current i radj C C ma internally limited temperatures junction temperature t j C 50 150 cC storage temperature t stg C 50 150 cC absolute maximum ratings (contd) C 40 c < t j < 150 c parameter symbol limit values unit remarks min. max.
tle 4470 semiconductor group 8 1998-11-01 note: in the operating range the functions given in the circuit description are fulfilled. operating range parameter symbol limit values unit remarks min. max. stand-by regulator input voltage v i 1 5.6 45 v C main regulator input voltage v i 2 v qnom + 0.6 v 45 v C stand-by regulator output current i q1 0 180 ma C main regulator output current i q2 0 350 ma C disable input voltage v dis C 0.3 45 v C sense input voltage v si C 0.3 17 v C junction temperature t j C 40 150 cC thermal resistances junction pin r thj-pin C 25 k/w measured to pin 4 junction ambient r thj-a C65k/wC
tle 4470 semiconductor group 9 1998-11-01 electrical characteristics v i 1 = v i 2 = 14 v; v dis < v disl ; C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max. stand-by regulator output 1 output voltage v q1 4.90 5.0 5.10 v 1 ma < i q1 <100ma output current limitation i q1 180 280 C ma see note 1 output drop voltage; v drq1 = v i 1 C v q1 v drq1 C 300 500 mv i q1 = 100 ma; see note 1 current consumption quiescent current; stand-by i q = i i 1 C i q1 i q C 180 250 m a i q1 = 300 m a; t j = 25 c v dis > v dish C 180 300 m a i q1 = 300 m a; v dis > v dish quiescent current i q = i i 1 C i q1 i q C46 ma i q1 = 100 ma regulator performance load regulation d v q1 C15 50mv1ma< i q1 <150ma; load regulation d v q1 C5 25mv1ma< i q1 <100ma; line regulation d v q1 C5 20mv i q1 = 1 ma; 6v< v i 1 <28v power-supply-ripple- rejection psrr C60 Cdb20hz< f r <20khz; v r = 5 v ss temperature output voltage drift d v q1 / d t C 0.3 C mv/k C d v i 1 /d t stability v q1 4.5 C 5.5 v no reset occurs; note 3 value of output capacitance c q1 6C C m fC esr of output capacitance r esrq1 CC 10 w at 10 khz
tle 4470 semiconductor group 10 1998-11-01 main-regulator output 2 output voltage tracking accuracy v q2 C v q1 C 25 5 25 mv 5 ma < i q2 < 100 ma; 6v< v i 2 <40v output voltage tracking accuracy v q2 C v q1 C 25 5 25 mv 5 ma < i q2 < 250 ma; 7v< v i 2 <28v see note 2 adjust input current i adj2 C 1 C 1 m aC output current limitation i q2 350 500 C ma see note 1 output drop voltage v drq2 = v i 2 C v q2 v drq2 C 300 600 mv i q2 = 200 ma; see note 1 current consumption quiescent current; i q = i i C i q i q C715ma i q2 = 200 ma i q1 = 300 m a quiescent current; i q = i i C i q i q C 250 500 m a i q2 = i q1 = 300 m a; t j = 25 c regulator performance load regulation d v q2 C5 25mv5ma< i q2 < 200 ma; line regulation d v q2 C5 20mv i q2 = 5 ma; 6v< v i 2 <28v power-supply-ripple- rejection psrr C60 Cdb20hz< f r <20khz; v r = 5 vss temperature output voltage drift d v q2 / d t C 0.5 C mv/k C d v i 2 /d t stability v q2 4.5 C 5.5 v no reset occurs; note 2 value of output capacitance c q2 10 C C m fC electrical characteristics (contd) v i 1 = v i 2 = 14 v; v dis < v disl ; C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 4470 semiconductor group 11 1998-11-01 esr of output capacitance r esrq2 CC 10 w at 10 khz disable input dis h-input voltage threshold v dish 1.8 2.0 2.3 v C l-input voltage threshold v disl 1.4 1.7 2.0 v output 2 active h-input current i dish C2 C 1 1 m a 2.3v< v dis <7v l-input current i disl C6 C2 C 0.5 m a 0v< v dis <1.4v reset timing d and output rq reset switching threshold v rt 4.5 4.65 4.8 v radj connected to gnd reset adjust threshold v radjth 1.25 1.35 1.45 v v q1 > 3.5 v reset output low voltage v rql C 0.15 0.3 v r rq = 10 k w external connected to v q1; v q1 3 1v reset high voltage v rqh 4.5 C C v C reset pull up resistor r rq 20 30 45 k w internal connected to v q1 reset charging current i d 359 m a v d = 1 v upper timing threshold v du 1.5 1.8 2.2 v C lower timing threshold v dl 0.3 0.4 0.55 v C reset delay time t d 12 15 20 ms c d = 47 nf reset reaction time t rr C0.52.0 m s c d = 47 nf electrical characteristics (contd) v i 1 = v i 2 = 14 v; v dis < v disl ; C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 4470 semiconductor group 12 1998-11-01 note 1: measured when the output voltage v q has dropped 100 mv from the nominal value. note 2: v q2 connected to adj2 note 3: square wave at v i : 8 v to 18 v; f = 10 khz; t r = t f 100 ns sense input si and output sq sense threshold voltage v sith 1.28 1.35 1.45 v v si decreasing sense threshold hysteresis v sihy 25 60 100 mv C sense output low voltage v sql C 0.15 0.4 v r sq = 10 k w external connected to v q1 v si = 1.1 v; v i 1 > 4.5 v sense output high voltage v sqh 4.5 C C v v si >1.5v sense pull up resistor r sq 20 30 45 k w internal connected to v q1 electrical characteristics (contd) v i 1 = v i 2 = 14 v; v dis < v disl ; C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 4470 semiconductor group 13 1998-11-01 application information figure 3 application circuit d c i c c r r 1n4004 zd1 si1 si2 si stand-by-regulator radjth main regulator ref 20 si sense reset = v d i = v dis 1 i v v 3 18 ref reference 19 8 4-7 14-17 aes02154 gnd 1 30 k w 9 30 k q1 v w radj sq rq 2 11 13 d adj2 12, 10 batt v d1 36 v 100 nf control 330 k w 10 nf 100 k w q2 22 f c 100 nf m q1 m 10 f c sith i 2 q2 q1 5 v 1 r r 2 ( = ) 10 v r 1 2 r pin numbers valid for p-dso-20-6 (tle 4470 g)
tle 4470 semiconductor group 14 1998-11-01 input, output the input capacitor c i is necessary for compensating line influences. using a resistor of approx. 1 w in series with c i , the lc circuit of input inductivity and input capacitance can be damped. to stabilize the regulation circuits of the stand-by and main regulator, output capacitors c q1 and c q2 are necessary. stability is guaranteed at values c q1 3 6 m f & c q2 3 10 m f, both with an esr 10 w within the operating temperature range. for the tle 4470 g (p-dso-20-6) the output voltage v q2 of the main regulator can be adjusted to 5 v v q2rated 20 v by connecting an external voltage divider to the voltage adjust pin va. for v q2 = 5 v the voltage adjust pin has to be connected directly to the main output. for calculating v q or r 1 & r 2 respectively the following equations can be used: v q = v ref ( r 1 + r 2 ) / r 2 or r 1 = r ( v q / v ref ) r 2 = r r 1 / ( r 1 C r ) definitions: r = r 1 // r 2 ; r ? 100 k w v ref = output voltage of stand by regulator, typical 5 v disable the main regulator of the tle 4470 can be switched off by a voltage of 2.3 v at pin dis. reducing this voltage below 1.4 v will switch on the main regulator again. reset timing the power-on reset delay time is defined by the charging time of an external capacitor c d which can be calculated as follows: c d = ( d t d i d ) / d v definitions: c d = delay capacitor d t d = delay time i d = charge current, typical 5 m a d v= v dt , typical 1.8 v v dt = upper delay switching threshold at c d for reset delay time the reset reaction time t rr is the time it takes the voltage regulator to set the reset out low after the output voltage has dropped below the reset threshold. it is typically 2 m s for delay capacitor of 100 nf. for other values for c d the reaction time can be estimated using the following equation: t rr ? 20 s/f c d
tle 4470 semiconductor group 15 1998-11-01 figure 4 reset timing reset switching threshold the internally set reset threshold is 4.65 v. when using the tle 4470 g (p-dso-20-6) this threshold can be adjusted to 3.5 v < v rth < 4.6 v by connecting an external voltage divider to pin radj. if this pin is not needed, it can be left open or even better connected to gnd. r 1 = r 2 ( v rt C v ref ) / v ref definitions: v rt = reset threshold v ref = comparator reference voltage, typical 1.35 v (reset adjust input current ? 50 na) the reset output pin is internally connected to the stand-by output q1 via a 30 k w pull-up resistor. the reset low signal at pin rq in guaranteed down to an output voltage v q1 of 1 v typical. aed01542 thermal t d power-on-reset voltage dip secondary overload at output spike v st v i v d v ro d i = v d dt v q rt v t rr < rr t v dt at input undervoltage shutdown c d
tle 4470 semiconductor group 16 1998-11-01 figure 5 early warning the early warning function compares a voltage defined by the user to an internal reference voltage. therefore the voltage to be supervised has to be scaled down by an external voltage divider in order to compare it to internal sense threshold (reference voltage) which is typically 1.35 v. the sense out pin is set to low when the user defined voltage falls below this threshold. a typical example where this circuit can be used is to supervise the input voltage v i to give the microprocessor a prewarning of a low battery condition. calculation of the voltage divider can be easily done since the sense input current can be neglected. to minimize transient influences the use of a capacitor in parallel to r 2 is recommended. like the reset output pin, the sense out pin sq is internally connected to the stand-by output q1 via a 30 k w pull-up resistor. the sense out low signal at pin sq is generated down to an input voltage v i1 of 3 v typical. aes02505 1 band-gap reference reference band-gap + _ radj ro q1 v v i1 gnd r 1 2 r 30 k w 1.35 v 1.35 v _ < tle 4470 g
tle 4470 semiconductor group 17 1998-11-01 typical performance characteristics drop voltage v dr versus output 1 current i q1 drop voltage v dr versus output 2 current i q2 output voltage v q1 / v q2 versus output current i q1 output 1 voltage v q1 versus temperature t j aed02491 0 0 = 125 ?c i v dr v dr 50 100 150 200 ma 300 100 200 300 400 500 600 = mv t j q1 j t = 25 ?c = -40 ?c t j off q2 v qnom v -0.1 v aed02492 0 0 = 125 ?c i v dr v dr 50 100 150 200 ma 300 100 200 300 400 500 600 = mv t j q2 j t = 25 ?c = -40 ?c t j qnom v -0.1 v aed02493 0 0 = 25 ?c i v q1 1 2 3 4 5 6 v t j q1 100 200 300 400 500 ma q1 v q2 v q2 v / aed02494 -40 4.6 = 13.5 v t v q1 4.7 4.8 4.9 5 5.1 5.2 v v i j 0 40 80 120 160 ?c
tle 4470 semiconductor group 18 1998-11-01 output voltage v q1 , v q2 versus input voltage v i ( v i1 = v i2 ) current consumption i q versus input voltage v i current consumption i q versus output 1 current i q1 (low load) current consumption i q versus output 1 current i q1 (high load) aed02495 0 0 = v v q 1 2 3 4 5 6 v v i i 24 6810 v q v q1 v / v q2 = 5 v v q2nom = q1nom v j t = 25 ?c = 10 ma i q1 q2 i = 10 ma aed02496 0 0 v i q 1 2 3 4 5 6 ma i v j t = 25 ?c 10 20 30 40 < 1 ma i q1 q2 i = 10 ma aed02497 0 0 = 25 ?c i i q 500 1000 2000 2500 3000 a t j q1 i v = 13.5 v off v q2 ma m 10 20 30 40 1500 aed02498 0 0 i i q 5 10 15 20 25 30 ma q1 50 100 150 200 250 ma q2 v off = 13.5 v v i j t = 25 ?c
tle 4470 semiconductor group 19 1998-11-01 current consumption i q versus output 2 current i q2 (low load) current consumption i q versus output 2 current i q2 (high load) reset adjust threshold v radjth versus temperature t j switching voltage v du , v dl versus temperature t j aed02499 0 0 = 25 ?c i i q 10 20 30 40 60 300 600 900 1200 1500 1800 a t j q2 i v = 13.5 v = 0 ma i q1 ma m aed02500 0 0 i i q 50 100 150 200 ma 300 5 10 15 20 25 30 q2 ma aed02501 -40 1.0 t v radjth 1.1 1.2 1.3 1.4 1.5 1.6 j 0 40 80 120 160 ?c v aed02502 -40 0 t v d 0.4 0.8 1.2 1.6 2.0 2,4 j 0 40 80 120 160 ?c = 13,5 v v i du v v
tle 4470 semiconductor group 20 1998-11-01 charge current i d versus temperature t j sense threshold v sith versus temperature t j aed02503 -40 2 t i d 3 4 5 6 7 8 j 0 40 80 120 160 ?c = 13.5 v v i d v = 1 v a m aed02504 -40 1 = 13.5 v t v sith 1.1 1.2 1.3 1.4 1.5 1.6 v v i j 0 40 80 120 160 ?c
tle 4470 semiconductor group 21 1998-11-01 package outlines 1.27 1.45 -0.2 17 8.75 -0.2 14 8 1.75 max 0.2 6 0.2 0.35 x 45? -0.2 4 0.1 -0.1 0.4 +0.8 index marking 1) +0.15 0.35 2) 2) does not include dambar protrusion of 0.05 max. per side 1) does not include plastic or metal protrusion of 0.15 max. per side 0.2 14x 1) 0.19 +0.06 8? max. gps05093 p-dso-14-4 (plastic dual small outline) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
tle 4470 semiconductor group 22 1998-11-01 p-dso-20-6 (plastic dual small outline) 110 11 20 index marking 1) does not include plastic or metal protrusions of 0.15 max per side 2) does not include dambar protrusion of 0.05 max per side gps05094 2.65 max 0.1 0.2 -0.1 2.45 -0.2 +0.15 0.35 1.27 2) 0.2 24x -0.2 7.6 1) 0.35 x 45? 0.23 8? max +0.09 +0.8 0.3 10.3 0.4 12.8 -0.2 1) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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